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Aldec
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Address:
2260 Corporate Circle
Henderson
NV 89074
USA
Telephone: (USA) +1 702 990 4400
http://www.aldec.com
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Listing of all 14 news releases from Aldec:
Integration support for co-simulation tools
Active-HDL coupled with The MathWorks Simulink provides support for fixed-point types and HDL co-simulation of black-boxes, which allows seamless integration with Simulink-based DSP tools
News from Aldec (13 April 2007)
Increased platform support from simulation tool
Support for Altera's Cyclone III devices in the latest release of Aldec simulators provides customers with access to the latest low-cost and low-power devices being offered by Altera
News from Aldec (22 March 2007)
Design verification support for devices
Aldec has announced System Verification Environment (SVE) support for Altera's new high-end Stratix III FPGA device family.
News from Aldec (13 November 2006)
Aldec Strengthens Verilog Simulator
Average performance gain of 57% on RTL and 250% on gate level and timing simulations
News from Aldec (19 October 2006)
Non-proprietary IP encryption methodology
Aldec has announced support for the Open IP Encryption Initiative design flow in the latest version of Aldec's Riviera tool.
News from Aldec (11 August 2006)
Design tools for ASIC and FPGA devices
Aldec, a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, has announced the addition of Expression Coverage for Verilog in the release of Rivieratm 2006.06.
News from Aldec (11 August 2006)
Hardware accelerators and prototyping tools
Aldec, a pioneer in mixed-language simulation, hardware accelerators and prototyping tools has been awarded a new patent for automatic conversion of ASIC designs into FPGA devices.
News from Aldec (25 May 2006)
Analysis of simulation results automated
Aldec, a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, has released Server Farm Manager (SFM).
News from Aldec (19 April 2006)
Simulator aimed at Linux design verification
Aldec, a pioneer in mixed-language simulation and advanced design tools for FPGA and ASIC devices, has released Riviera-SNA (Simulator for Networking Applications).
News from Aldec ( 3 August 2005)
System-level simulation performance and debugging
Aldec has announced the release of Riviera 2005.04 with an all new system-level simulation engine and improved SystemC debugging.
News from Aldec (19 April 2005)
Smart clocking with improved memory handling
Aldec, a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, has released Riviera-IPT with all-new support for the ARM926 hardcore processor.
News from Aldec ( 8 March 2005)
Debugging and verification abilities strengthened
Aldec has released Riviera 2004.12 that includes additional SystemC debugging features, enhanced OVA/PSL/SVA assertion-based verification (ABV), and operating system-independent design libraries.
News from Aldec (30 December 2004)
Seamless design flow interface
Aldec, together with Magma Design Automation, has announced the completion and immediate availability of the design flow interface between Active-HDL 6.3 and PALACE version 2.4.
News from Aldec (24 November 2004)
Riviera-IPT with Co-Verification support for Arm
Riviera-IPT provides a seamless, high-speed co-verification and debug environment for complex embedded software/hardware co-development utilizing the Arm processors.
News from Aldec (18 June 2004)
