Product category:
Measurement and Quality Software and SPC
News Release from: Aldec
Edited by the Manufacturingtalk Editorial
Team on 11 August 2006
Design tools for ASIC and FPGA devices
Aldec, a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, has announced the addition of Expression Coverage for Verilog in the release of Rivieratm 2006.06.
Aldec, a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, has announced the addition of Expression Coverage for Verilog in the release of Rivieratm 2006.06 This addition significantly improves efficiency of the verification process and enables delivery of higher quality, more reliable designs
This article was originally published on Manufacturingtalk on 13 Apr 2007 at 8.00am (UK)
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"As more time and resources are allocated to testbench development, reliable feedback on the effectiveness becomes indispensable in the verification process," states David Rinehart, Vice President of Aldec.
"We continue to see more organizations not only relying on coverage analysis for this feedback, but harnessing the results to create dynamic testbenches that shrink development cycles while increasing product quality." Although frequently used statement coverage can provide valuable feedback to the designer, it only informs whether the expression in the statement was evaluated.
Expression Coverage provides more information: all meaningful combinations of expression operands are counted during simulation, allowing detection of problems that could easily go undetected using other coverage analysis methods.
Expression Coverage is similar to other forms of code coverage, but provides a much finer granularity of coverage metrics than statement, toggle, or branch coverage analysis, which are also included in Riviera.
With Expression Coverage, for each logic expression in Verilog code, a set of cases is identified and each case specifies one of the total possible combinations of inputs to the expressed logic.
Expression coverage then considers whether a simulation run exercises each case of the expression.
An expression is fully covered when all of the individual expression coverage cases are exercised.
Additional improvements in Riviera 2006.06 include faster Verilog and VHDL compilation and simulation; PSL assertions embedded in VHDL code for improved verification, communication and IP correct usage detection; Synplicity Protected flow for IP protection; and numerous GUI enhancements.
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