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Product category: Measurement and Quality Software and SPC
News Release from: CoWare
Edited by the Manufacturingtalk Editorial Team on 21 July 2006

Building blocks compatible with
architecture

Arteris and CoWare have announced that Arteris will output SystemC transaction level models (TLM) from its NoC tool suite for incorporation into TLM platforms developed in CoWare Platform Architect.

Arteris, the technology leader for Network-on-Chip (NoC) technology and solutions, and CoWare, the leading supplier of platform-driven electronic system-level (ESL) design software and services, announced a comprehensive agreement under which Arteris will output SystemC transaction level models (TLM) from its NoC tool suite for incorporation into TLM platforms developed in CoWare Platform Architect As part of the collaboration, the companies will develop IEEE 1666 SystemC-based versions of the Arteris NoC building blocks that are compatible with CoWare's Platform Architect environment

Designers can utilize the Arteris tool suite to create RTL of the NoC, complete with synthesis scripts and test bench models, and then profile, debug and simulate both SoC hardware and embedded software implementations before silicon implementation.

The Arteris tool set enables near real-time interaction and is driven by a familiar "spreadsheet" style of design.

"On-chip communications decisions are best made during the system-level design stage and this is an area where CoWare is a proven leader," said Charlie Janac, president and CEO of Arteris.

"By incorporating the ability to design and analyze a NoC approach at this point in the design cycle, we are enhancing the designer's ability to maximize performance and integration benefits of SoC design in general and network-on-chip in particular.

With the powerful combination of CoWare ESL design and advanced Arteris NoC technology, we will help lower both unit costs and project costs of complex SoCs for multi-media, telecom, and wireless applications." The Arteris NoC methodology offers significant benefits to SoC designers who are developing complex chips using multiple IP and multiple processors, and are driving performance beyond 200 Mhz.

For those chips, traditional bus-based architectures are fraught with timing closure, power consumption, and area problems that get increasingly difficult if not impossible to solve as process geometries dip to 90nm and below.

At such density levels, gates are faster than wires and the Arteris NoC solution addresses the inherent challenges in bus-based designs.

By integrating the Arteris technology with CoWare's ESL design tools, developers of complex SoCs have a complete solution for high-level design and NoC integration.

"The addition of Arteris NoC to the CoWare model library provides an unprecedented way to handle the vexing problems found in leading-edge SoCs," said A.K.

Kalekos, vice president of marketing and business development for CoWare.

"These problems include multiple IP and processors, clock domains, and wire and bus constraints.

Now these problems can be solved within the best ESL design environment available today.

We welcome Arteris as a supplier of critical, next-generation NoC technology.".

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