Product category:
Programming aids and applications
News Release from: JTAG Technologies | Subject: 1149.6 Testing with Diagnostics Boundary-scan
Edited by the Manufacturingtalk Editorial
Team on 24 November 2006
Boundary scan support for PCB testing
JTAG Technologies, leading provider of boundary-scan solutions, has announced the industry's most complete support for PCB and systems testing based on IEEE standard 1149.6.
JTAG Technologies, leading provider of boundary-scan solutions, has announced the industry's most complete support for PCB and systems testing based on IEEE standard 1149.6 for advanced digital networks IEEE 1149.6 (or 'dot6') is an important extension to the original 1149.1 (or 'dot1') boundary-scan specification and eliminates test restrictions associated with high-speed digital interfaces such as LVDS (low-voltage differential signalling) and AC-coupled networks
This article was originally published on Manufacturingtalk on 10 Apr 2006 at 8.00am (UK)
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Prior to "dot6", testing these types of networks could produce erroneous pass/fail indications.
For example, the high levels of fault-tolerance implicit in differential networks could allow faults to escape detection if using normal 1149.1 techniques.
A circuit with a misplaced, or wrong value, terminating resistor might work at low-speed and thereby pass the dot1 testing but would fail at the high speeds of normal operation.
Conversely, the DC-blocking effects of AC-coupling can result in dot1 test failures with results that resemble open circuit faults.
Both of these shortcomings are addressed by the IEEE 1149.6 standard that includes provision for fast pulse generation and detection circuits at each pin within a compliant device.
JTAG ProVision software from JTAG Technologies automatically produces an exhaustive test for these types of advanced digital interfaces based upon the netlist of the circuit and the 1149.6 BSDL (device model) files for the compliant components in the design.
Significantly, the JTAG ProVision dot6 test produces a diagnostic fault report that pinpoints the cause of the failure, including isolation of individual faults should multiple faults occur.
The fault report can also be further analysed by JTAG Visualizer, the schematic and layout viewer from JTAG Technologies, and is presented to the engineer as a colour-highlighted graphical output. Request a free brochure from JTAG Technologies ...
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