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News Release from: Lattice Semiconductor UK | Subject: IspLEVER-Starter
Edited by the Manufacturingtalk Editorial
Team on 09 February 2005
Logic design tools now available via
free download
Lattice ispLEVER- Starter design tools now support selected LatticeEC FPGA devices
Lattice Semiconductor has announced the immediate availability of Version 4.2 of its web-downloadable ispLEVER-Starter programmable logic design tool suite The ispLEVER-Starter tools are a complete programmable logic design environment supporting HDL design entry and management, synthesis, place and route, and on-chip debug for Lattice's newest, most popular programmable products
This article was originally published on Manufacturingtalk on 24 May 2005 at 8.00am (UK)
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For the first time, the ispLEVER-Starter tools support selected members of Lattice's recently introduced high performance, low-cost LatticeEC FPGAs.
These tools provide a no-risk gateway for designers eager to create system-level solutions using this exciting new Lattice FPGA family.
The ispLEVER-Starter design tools are a complete programmable design tool solution intended for initial technology evaluation, students and other programmable logic users who require low- to medium-scale integration.
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The tools are available for download from www.latticesemi.com/starter.
These tools are available as modules, so the user need only download the required portions of the software.
The ispLEVER-Starter modules include:.
* Primary module: This required module contains the main ispLEVER engine, and includes design support for some of Lattice's newest and most popular CPLD products, such as the ispMACH 4000 families.
* LatticeEC Module: This optional module includes the design tools and device libraries required to complete a design for the LatticeEC1 and EC3 FPGAs.
The LatticeEC1 is a 1.5K Look-Up Table (LUT) FPGA with 18 kilobits of Embedded Block RAM (EBR), 2 Phase-Locked Loops (PLLs) and up to 112 I/O pins.
The LatticeEC3 device is a 3.1K LUT FPGA with 55 kilobits of EBR, 2 PLLs and up to 160 I/O pins.
* Five additional, larger members of the Lattice EC family ranging from 6.1K LUTs (LatticeEC6) to 32.8K LUTs (LatticeEC33) are currently available.
These devices, along with the LatticeEC1 and EC3, are supported by the Base and Advanced versions of Lattice's ispLEVER tools available for sale from Lattice distributors worldwide.
* ispXPGA Module: This optional module includes the design tools and device libraries required to complete a design for any Lattice ispXPGA non-volatile FPGA device, from the 2K LUT LFX125 to the 15.4K LUT LFX1200.
* LeonardoSpectrum Synthesis Module: This module enables the designer to target and synthesize HDL designs for Lattice programmable technologies using the LeonardoSpectrum synthesis tool from Mentor Graphics.
* Synplify Synthesis Module: This module enables the designer to target and synthesize HDL designs for Lattice programmable technologies using the Synplify for Lattice synthesis tool from Synplicity.
* Help and User Guides Module: This optional module includes the Help and User Guides for ispLEVER-Starter.
The ispLEVER 4.2 SP1 - Starter design tools are available now for download at no charge from www.latticesemi.com/starter.
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