Product category:
Manufacturing IT hardware
News Release from: Lattice Semiconductor UK
Edited by the Manufacturingtalk Editorial
Team on 03 March 2005
Low-cost, Flash-based non-volatile FPGAs
No compromise Flash-based LatticeXP FPGAs are instant-on and infinitely reconfigurable - Devices move swiftly to market with immediate availability of first device samples
Lattice Semiconductor Corporation has announced its new LatticeXP devices, which combine a low-cost FPGA architecture with non-volatile, infinitely reconfigurable ispXP (eXpanded Programmability) technology The LatticeXP devices deliver the benefits of instant-on operation, excellent security and a single-chip implementation and provide cost-effective alternatives to SRAM-based FPGAs and their associated boot memories
This article was originally published on Manufacturingtalk on 6 May 2005 at 8.00am (UK)
Related stories
Lattice Announces ispLEVER 5.0
Unprecedented ease-of-use, new features and exceptional performance - full design support for all Lattice digital programmable logic devices includes the new LatticeXP FPGA family.
Standby Power Reduced to Under 120uA
Lattice Reduces Standby Current for LatticeXP FPGA Family by a Factor of 1000
Through advanced 130nm Flash silicon technology, an optimized architecture and proprietary circuit design, die sizes of the new LatticeXP devices have been reduced over 80% compared to the previous generation of Lattice non-volatile FPGAs.
First samples of the 10K Look-Up Table (LUT) LatticeXP10 device are now available with the remaining 4 family members planned for second quarter availability.
"Lattice first delivered volume, non-volatile FPGAs to the marketplace in 2003, and our customers responded positively," said Cyrus Tsui, Lattice Chairman and CEO.
Further reading
Design services company chooses LatticeXP
Non-volatile FPGA's capacity, power consumption, space saving and cost cited
Lattice Semiconductor To To Support Fujitsu
Lattice Semiconductor Corporation has announced an agreement to advance US$125 million in support of the new 300mm silicon wafer fab being constructed by Fujitsu Limited in Mie, Japan.
IP Cores Implement CAN Bus and IEEE 1394
Lattice Semiconductor Corporation and its IP partner, CAST Incorporated, have announced intellectual property (IP) support for the new LatticeECP-DSP and LatticeEC FPGA device families.
"However, customers also told us that to expand their use of this ultimate FPGA technology they required prices more consistent with that of SRAM-based FPGAs plus the associated boot PROMs.
This new generation of LatticeXP products makes non-volatility finally affordable for the growing number of users who prefer a non-volatile solution.
This unmet demand represents a large opportunity for Lattice that has not been addressed by the dominant FPGA market players." LatticeXP devices are implemented on a cost effective, low-k, 130nm CMOS Flash process using copper metallization.
The technology was co-developed by Fujitsu Limited and Lattice Semiconductor.
Production wafers are fabricated by Fujitsu in their state-of-the-art wafer fab.
The devices support operation from 1.2-, 1.8-, 2.5-, or 3.3-volt power supplies.
The ispXP technology used in the LatticeXP devices combines SRAM and non-volatile Flash memory to deliver an FPGA that is both non-volatile and infinitely reconfigurable.
"Customers have told us that the concept of a non-volatile, infinitely reconfigurable FPGA, with its associated one-chip solution benefits of instant-on operation and security, represents the FPGA promised land," said Stan Kopec, vice president of marketing for Lattice.
"With such an FPGA, customers would have the best of both worlds: the infinite reconfigurability of SRAM and the many benefits of non-volatility.
"Now the concept is reality," Kopec continued.
"We believe the LatticeXP will rapidly become the no compromise FPGA for cost-conscious, high-volume applications." The SRAM-based memory cells control the operation of the device logic and are loaded from the on-chip Flash memory in less than 1mS at power-up, providing instant-on capability, or boot up on user command.
The products can also be configured via a microprocessor interface, referred to as the sysCONFIG interface, or the JTAG interface.
Unlike traditional SRAM-based FPGAs, the LatticeXP device does not require an external boot memory and so provides a single-chip solution with the associated benefits of reduced board area and simplified system manufacture.
The absence of an external boot device also eliminates the need for an external bit-stream at boot up and the possibility of bit-stream snooping, a major security concern with SRAM FPGAs.
Security features prohibit bit-stream readback from the SRAM and Flash sections of the devices to further enhance security.
The LatticeXP architecture was developed concurrently, and from the "ground up," with that of the previously announced LatticeECP/LatticeEC FPGAs.
As with the low-cost LatticeECP/EC devices, all LatticeXP architectural elements such as logic blocks, I/O capabilities including DDR support and embedded memory, among others, were evaluated in the context of their targeted high-volume applications as the devices were defined.
The feature sets were then precisely sculpted to be neither excessive (driving up cost) nor "bare bones" (limiting the application range) in order to maximize their broad adoption.
The resulting combination of a superior streamlined architecture, compact circuit design and production-proven technology found in the LatticeXP devices allows them to provide the benefits of non-volatile, infinitely reconfigurable FPGAs and to be cost-effective alternatives to SRAM-based FPGAs and their associated boot memories.
The LatticeXP devices will be offered in a range of 5 densities, from 3K to 20K LUTs.
The devices provide I/O counts from 62 to 340 in a variety of low-cost Plastic Quad Flat Pack (PQFP), Thin Quad Flat Pack (TQFP) and 1mm fine-pitch Ball Grid Array (fpBGA) packaging.
A closer look: LatticeXP optimised architecture.
* Based upon industry-standard, synthesis-friendly 4-input look-up table (LUT) logic blocks.
* Twenty-five percent of the logic blocks contain distributed memory, an optimization that reduces cost while supporting the vast majority of application requirements for small amounts of distributed memory.
* The availability of sysCLOCK Phase Locked Loops (PLLs) and Embedded Block RAMs (EBRs) allows designers to reduce costs further by integrating these functions within the FPGA, eliminating external discrete devices.
* Advanced sysI/O buffer capability supports standards such as LVCMOS, LVDS, LVTTL and PCI, as well as SSTL and HSTL, allowing users to easily and efficiently interface to the industry's most popular bus standards.
These standards were carefully selected to maximize application range while minimizing die area.
* The LatticeXP devices have dedicated circuitry to simplify DDR memory interfaces, while providing the highest performance, integration, signal integrity and ease of design for FPGAs in this class.
DDR memory has become the low-cost memory of choice: estimates suggest DDR represented 75% of DRAM bits shipped in 2004, up from 39% in 2002.
In addition to a common FPGA architecture, the LatticeEC, LatticeECP and LatticeXP devices share a common design methodology and design tool flow supported by the Lattice ispLEVER design tool suite.
Lattice ispLEVER software provides designers with access, in one software package, to all Lattice digital devices and includes synthesis support using Mentor Graphics Precision RTL and Synplicity Synplify design tools.
The ispLEVER Version 4.2 Service Pack 1 provides initial LatticeXP support.
An extensive range of IP (intellectual property) cores, particularly suited for high-volume applications, will be available from both Lattice and its IP partners.
Complete details of IP support will be announced throughout 2005.
• Lattice Semiconductor UK: contact details and other news
• Email this article to a colleague
• Register for the free Manufacturingtalk email newsletter
• Manufacturingtalk Home Page
Search the Pro-Talk network of sites
