Lattice releases Rake Receiver reference design

Lattice releases Rake Receiver reference design for low-cost LatticeECP-DSP FPGAs

Lattice Semiconductor Corporation has announced the immediate availability of its Rake Receiver reference design, targeted at base stations in wireless telecom applications.

A Rake Receiver is used to counter the effects of RF multipath fading due to atmospheric absorption, ionospheric reflection and refraction, and reflection from terrestrial objects such as mountains and buildings.

The technique uses several sub-receivers, each delayed slightly, in order to tune in the individual multipath components and then combine them to optimize the signal reception.

The reference design uses the new LatticeECPTM (EConomy Plus) FPGAs that combine an optimized FPGA fabric with high-speed, dedicated DSP blocks on-chip.

"LatticeECP-DSPTM FPGAs are ideal for applications in which cost-effective DSP functionality is needed," said Stan Kopec, Lattice vice president of corporate marketing.

"Our new Rake Receiver reference design is specifically designed to take advantage of the device family's embedded DSP support, delivering high-speed channel correction in a low-cost FPGA fabric.

This W-CDMA solution is another example of Lattice 'Bringing the Best Together' with unique silicon plus application expertise that gets our customers to market fast," Kopec added.

Lattice ispLever v4.2 design software supports the ECP family for design entry, simulation, and place and route.

In addition, the reference design includes a model of the Rake Receiver generated using The MathWorks Matlab.

The model supports data generation and simulation capabilities in the popular Matlab environment.

The reference design has the following features (one instance of the rake engine):.

* 61.44Mhz operating frequency.

* Interpolation of 2 times over-sampled input data to 1/16 of a chip resolution.

* Handles 16 control channels and 16 data fingers.

* Simultaneous generation of 16 scrambling codes at chip rate.

* Simultaneous generation of 16 Orthogonal Variable Spreading Factor (OVSF) codes.

* De-scrambling and dispreading of input signals with 16 different delays.

* Channel correction (de-rotation and scaling) of de-scrambled and de-spread signals.

* Combining of multiple de-scrambled, de-spread and channel-corrected signals from a variable number of fingers.

* Independent early-late gate based symbol timing tracking based on each of 16 control channel signals.

* Uses 18x18 multiply-accumulate DSP feature of LatticeECP FPGAs.

* Time slicing hardware to support 16 rake fingers per "engine".

* Time slicing exploits distributed RAM capability (16x1 bits per LUT) for the context switching between 16 fingers.

* Uses a time-sliced "Farrow Interpolator" to interpolate input data by a factor of 8.

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