Upgraded design tools available at no charge

Lattice ispLEVER-Starter design tools now support all LatticeEC FPGA devices

Lattice Semiconductor Corporation has announced that its upgraded ispLEVER-Starter 5.0 design tools can now be downloaded from the Lattice website.

ispLEVER-Starter 5.0 is offered free of charge in order to encourage easy evaluation of Lattice's recently announced ispLEVER 5.0 programmable logic design tool suite.

ispLEVER-Starter 5.0 uses the same interface and design flow as ispLEVER 5.0, and can be used to take a design from concept to device programming.

Like previous ispLEVER-Starter design tools, ispLEVER-Starter 5.0 supports all Lattice ispXPGA FPGAs, CPLDs, ispGDX and SPLD devices.

The PC-based ispLEVER-Starter 5.0 tools also now include design support for all low cost LatticeEC FPGAs as well as the LatticeECP-DSP6 device.

This expanded design support gives users unprecedented access to Lattice's newest low cost FPGAs.

"The LatticeEC family, with 7 family members ranging in density from 1.5K to 33K LUTs, is being used in designs around the world," said Stan Kopec, Lattice vice president of corporate marketing.

"With design support for the entire product line so accessible, every design engineer worldwide will be able to evaluate our technology and its advantages first-hand." Many features and performance enhancements have been added with the release of ispLEVER 5.0-Starter, including:.

* Production support for the LatticeECP/EC low cost FPGAs.

* Support for ALL Lattice FPGA, FPSC, CPLD and SPLD device families (even those previously offered only in Advanced ispLEVER configurations).

* Significant performance improvements including FIFO performance increased by 50-70%, LatticeECP DSP block performance is substantially faster and device resources used have been reduced by an average of 5%.

* Extensive documentation and help additions and enhancements.

* Significantly enhanced FPGA floorplanning flow.

* New DSP building blocks and design features, including subsystem parameterization.

* In-system logic analysis improvements with the ispTRACY tool.

* Fully integrated Precision RTL 2005a synthesis from Mentor Graphics.

* Synplify 8.0b synthesis from Synplicity.

* Dozens more major additions and improvements to nearly every aspect of the design flow.

A full list of ispLEVER 5.0 features and enhancements can be seen at http://www.latticesemi.com/products/devtools/software/isplever50.cfm The ispLEVER 5.0-Starter design tools are available now at no charge and can be downloaded from www.latticesemi.com/starter.

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