IspLever 5.1 programmable logic design tool suite

New FPGA preference flow provides designers with greater flexibility and control

Lattice Semiconductor Corporation has announced the immediate availability of its ispLever 5.1 programmable logic design tool suite.

Version 5.1 implements many new features and delivers enhanced performance.

For example, Lattice FPGA logic utilization has been increased by as much as 35%, while design operating frequencies have been boosted up to 25%.

A new IP delivery infrastructure called IPexpress is included that allows designers to quickly configure Lattice system-level IP for their designs.

The ispLever 5.1 release also introduces significant improvements to the FPGA design process, allowing designers to work more efficiently, improve productivity and speed time to market.

The ispLever 5.1 software introduces a new FPGA design preference flow that gives more control to the designer.

Design preferences that dictate how an FPGA design will be implemented in Lattice silicon are no longer tied to a particular stage in the design process.

The FPGA designer can make changes to design preferences at any point, from the initial stage of HDL source code to final place and route, and is assured of greater consistency throughout the entire design process.

"The new IPexpress infrastructure and our new FPGA design preference flow are two significant design productivity improvements that transform our ispLever software into a more powerful tool for our customers," said Chris Fanning, Lattice vice president of software and IP solutions.

"Our customers face tremendous time to market pressures and ispLever 5.1's enhanced flow and performance capabilities will significantly improve their productivity and results." The ultimate measure of design tools performance is the quality of design results.

The ispLever 5.1 software introduces significant improvements in the maximum operating speed of designs (fMAX average), as well as the efficiency of silicon resource usage (LUT and SLICE utilisation).

Using techniques that include timing-driven mapping and congestion-driven placement, device logic resource usage has been reduced by as much as 35%, and silicon performance increased up to 25%.

These improvements can ultimately translate into lower-cost solutions for customers, as their designs can frequently fit into smaller and lower speed grade Lattice FPGAs.

"Performance and utilisation improvements in ispLever 5.1 further enhance our world-class FPGA design solution," said Stan Kopec, Lattice vice president of corporate marketing.

"The performance and productivity gains enabled by ispLever 5.1 ensure that our customers can achieve their design goals more easily and at lower cost." Industry leading synthesis and simulation Lattice continues to be the only programmable logic company to include industry-recognised best-in-class synthesis and simulation tools with every Windows-based ispLever installation.

Ongoing collaboration among Lattice and EDA industry leaders Synplicity and Mentor Graphics provides HDL synthesis and simulation tools optimised for Lattice products.

The ispLever 5.1 release includes new versions of Synplicity Synplify for Lattice (v8.2c), and the Mentor Graphics PrecisionRTL (2005b) synthesis tools, as well as the Mentor Graphics ModelSim version 6.1a simulation tool.

The ispLever 5.1 software also includes new device libraries that expand support for additional EDA tools, including simulation tools from Cadence (NC-Verilog) and Synopsys (VCS), and new DSP design elements for the MATLAB/Simulink design environment from The MathWorks.

Intellectual Property (IP) cores are now commonly used in FPGA designs.

The ispLever 5.1 software includes a new infrastructure that will dramatically improve the way Lattice customers access and utilize IP.

The IPexpress infrastructure will allow users to parameterize IP quickly and easily, without factory assistance.

The IPexpress infrastructure provides a single easy-to-use gateway to industry standard, user-configurable functions that have been optimized for maximum performance in Lattice silicon products.

Dozens of improvements to all ispLever tools, including:.

* New design support for the LatticeXP 15 and LatticeXP 20 Flash-based FPGAs.

* New design support for the MachXO 1200 and MachXO 2280 Flash-based crossover PLDs.

* Help and search capabilities have been significantly expanded and made faster, topics have been re-indexed and new design tutorials added.

* New file extract feature for schematic symbol generation is compatible with most industry standard Schematic/PCB tools.

* New constraint options give designers more control of how their logic designs are implemented and optimized for Lattice silicon.

* New ispLever DSP blocks and modules.

* The Lattice News Panel gives designers instant access to relevant news about Lattice silicon and software products.

A complete list of the new features and enhancements to the ispLever 5.1 design tool suite can be viewed at.

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