Programmable zero-delay clock generator

Lattice Semiconductor expands its revolutionary ispClock family with programmable zero-delay clock generator devices.

Lattice Semiconductor Corporation has announced its new ispClock second generation family of enhanced zero-delay clock generators, the ispClock5600A devices, along with the availability of the first device, the ispClock5620A.

The programmable, E2CMOS-based ispClock5620 devices can generate up to 20 clock outputs, each with independently programmable output skew, I/O standard and frequency selection.

The non-volatile, in-system programmable ispClock5600A devices are pin compatible with Lattice's first generation ispClock5600 devices, but provide a number of significant additional features and parametric enhancements.

Heading the list of significant enhancements, the maximum VCO operating frequency of the ispClock5600A devices has been increased to 800 MHz.

This supports the generation of popular clock frequencies such as 33.33MHz, 100 MHz, 133.33 MHz and 50 MHz simultaneously from a single master frequency.

The input clock frequency range has been extended (5 MHz to 400 MHz) to enable support at 8.192 MHz, a popular telecom clock frequency.

Additionally, the device's Universal Fan-out Buffer is able to source clocks to DDRII and QDRII memories (up to 400 MHz).

"Our ispClock5600A devices substantially reduce clock network design effort," said Stan Kopec, Lattice corporate vice president of marketing.

"Traditionally, as the performance requirements of the system increased, the effort required to generate and distribute clocks grew exponentially".

"Our programmable ispClock5600A devices provide unprecedented convenience to designers without compromising the system specifications".

"The devices provide faster time to market, reduced board space and improved manufacturability and reliability." The ispClock5600A devices use seven on-chip counters (input, feedback and five for outputs) to provide fine granularity output frequency generation.

The high-performance Universal Fan-out Buffer has a maximum pin-to-pin skew of 50ps, regardless of bank and frequency, while the maximum cycle-cycle (peak-peak) output jitter is less than 70ps, and the period jitter less than 12ps (rms).

The output skew of each clock net relative to the reference input can be further controlled in delay increments of 156ps (lead or lag) to compensate for differences in circuit board clock network trace length.

In addition, both the reference input and the Universal Fan-out Buffers can support a wide variety of popular single-ended and differential logic standards (LVCMOS, LVTTL, HSTL, SSTL, LVDS, LVPECL, Differential HSTL, Differential SSTL) at a variety of voltage levels.

The input termination and output impedance of each output can be individually tuned to match each trace impedance, resulting in clock nets with high signal integrity.

Increase Timing Margin in Line Card Designs.

The Static Phase Offset specification of the ispClock5600A devices is less than 100 ps; consequently, these devices are ideally suited for applications that require local circuit board clocks to align their phases to a central backplane clock (for example, Advanced TCA and Medical Instrumentation), or to distribute a master clock to a wide variety of ASICs and FPGAs interfacing to the CPU Bus.

Single Chip Generates Clocks for QDR II and DDR II Memory.

Many communication boards use both QDRII and DDRII memories, and the ispClock5620A device provides a single chip solution.

The Universal Fan-out Buffer of the ispClock5600A device can be independently configured for the Differential HSTL standard (for QDR II) or for the Differential SSTL standard (for DDR II).

Additionally, the clock frequency also can be independently set for both these output standards depending on the speed of the memory used in a design.

Simplify Clock Network Layout by Compensating for Timing Delays.

Clock network routing is constrained to maintain timing integrity across multiple devices connected to the same clocking network.

Designers typically resort to serpentine patterned traces to accommodate the extra length clock traces.

Because the output of a clock edge can be skewed precisely with an ispClock5600A device, designers can route the clock patterns as required, and the clock edge arrival delay due to unequal clock trace lengths can be compensated for.

Reduce Circuit Board EMI Emission by Staggering Clock Edges.

To meet strict EMI standards, designers commonly resort to using spread spectrum clocks.

Spread spectrum clocks intentionally introduce jitter to diffuse peak power emission due to coincident clock edges across multiple devices.

However, increased jitter is not desirable in many applications.

The fine output skew feature of the ispClock5600A device enables designers to stagger the clock edge in steps of approximately 156ps, spreading the clocking edge without introducing jitter: a superior method to control the EMI emission of a circuit board.

The Lattice Windows-based design software, PAC-Designer Version 4.1, provides comprehensive design support for the ispClock5600A device family.

In addition, utilities such as Graphical Skew Editor, Frequency Calculator and Frequency Synthesis support have been enhanced to address a wider range of application issues.

Design configurations can be downloaded quickly into ispClock5600A devices via the PC parallel port.

This version of the PAC-Designer software can be downloaded free from the Lattice Semiconductor website.

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