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News Release from: Lattice Semiconductor UK | Subject: EConomy Plus
Edited by the Manufacturingtalk Editorial
Team on 10 February 2006
Lattice expands market for low cost
FPGAs
Second generation EConomy Plus devices expand concept by reducing prices 50% and doubling available density.
Lattice Semiconductor Corporation has introduced its second-generation EConomy Plus Field Programmable Gate Array (FPGA) devices, the LatticeECP2 family Developed on 90nm Fujitsu CMOS technology utilising 300mm wafers, this family cuts FPGA prices to under $0.50 per 1,000 Look-up Tables (LUTs) in high volume
This article was originally published on Manufacturingtalk on 6 Oct 2004 at 8.00am (UK)
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Compared to Lattice's first-generation 130nm LatticeECP FPGAs, the new family also increases available logic density to 70K LUTs, increases the number of 18x18 multipliers to 88, boosts I/O performance over 50% and enhances configuration capabilities.
Capabilities added for the first time to this class of FPGAs include pre-engineered 400Mbps DDR2 memory interface support, configuration bitstream encryption and dual-boot configuration support.
Lattice's low cost LatticeECP2 devices are being announced today simultaneously with its high-end LatticeSC System Chip FPGAs, fabricated on the same technology.
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"Lattice customers have enthusiastically welcomed the Economy Plus concept that Lattice pioneered with its first-generation LatticeECP family," said Stan Kopec, Lattice corporate vice president of marketing.
"The enhancements that LatticeECP2 brings in the areas of logic and memory capacity, I/O performance and configuration flexibility allow this new family to capture many new designs that would otherwise need to be targeted at higher cost, full-featured FPGAs." Throughout their development, the LatticeECP2 devices have been optimised to deliver the features and cost structure required by designers for high-volume applications.
Key points include: Optimised Logic and Routing Fabric: The logic block and routing have been optimised to tailor features such as distributed memory (provided on 12.5% of LUTs) and registers (provided on 75% of LUTs) to the typical application set.
The resulting logic fabric allows easy high performance logic implementation.
Pre-engineered 840Mbps Parallel I/O: The rise of DDR memories and other similar standards leaves many designers grappling with the challenge of implementing high performance parallel I/O interfaces within FPGAs.
To meet this need designers have historically had to utilise high cost FPGA solutions.
The ECP2 devices provide DDR mux/de-mux, precision delay and gearbox logic elements.
These can be combined to implement pre-engineered DDR2 (400Mbps) and other source synchronous interfaces operating at up to 840Mbps for applications such as SPI4.2 and ADC/DAC interfaces.
Full Feature sysDSP Blocks: To support low cost DSP applications, the ECP2 devices embed sysDSP blocks capable of implementing multiply, accumulate, summation and pipelining functions.
The devices can implement DSP functions up to 28,600 Million Multiply Accumulates per second (MMACs) at prices below $.001 per MMAC.
Easy Field Logic Update: In order to accommodate bug fixes, respond to standard changes and support the addition of new features and services, an increasing number of FPGA designs require FPGA logic update in the field.
The LatticeECP2 provides dual-boot support and Transparent Field Reconfiguration (TransFR) I/O to simplify field updates.
The devices also support the storage of two or more configurations in industry standard Serial Peripheral Interface (SPI) PROMs.
TransFR I/O capability allows designers to precisely control I/O states while a new configuration is loaded into the FPGA, a significant improvement over the more conventional practice of tri-stating I/Os during reconfiguration.
Bitstream Encryption for Enhanced Design Security: To address increasing design piracy concerns, the LatticeECP2 devices have on chip non-volatile key storage and decryption circuitry to allow the decryption of 128-bit AES encrypted bitstreams based on a unique user key.
This brings the concept of bitstream encryption to low-cost SRAM FPGA products for the first time, again reducing the need for higher cost FPGAs in many designs.
The LatticeECP2 family will be offered in two versions, the standard LatticeECP2 and a memory enhanced (LatticeECP2M) version to be announced later in 2006.
The LatticeECP2M devices will increase density to 100K LUTS and enhance memory capacity to over 5million bits of RAM.
In all, 6 device densities from 6K to 70K LUTs are planned for the LatticeECP2 family plus additional members of the LatticeECP2M family.
The LatticeECP2 devices will provide between 55K and 1Mbit of embedded memory through sysMEM Embedded Block RAM (EBR), twelve to eighty-eight 18x18 multipliers and 95 to 628 I/O pins.
In addition, each device provides two Delay Locked Loops (DLLs) and from 2 to 6 Phase Locked Loops (PLLs) for timing control.
The parts will be available in a variety of low-cost TQFP, PQFP and fine pitch BGA (fpBGA) packages and operate from 1.2volt power supplies.
Design support for the LatticeECP2 devices is provided by the latest version of the ispLEVER tool suite, Version 5.1 using Service Pack 2.
These ispLEVER design tools provide designers with access, in one software package, to all Lattice digital devices and include synthesis support from Mentor Graphics and Synplicity.
An extensive range of IP (Intellectual Property) cores, particularly suited for high volume applications, will be available from both Lattice and its IP partners.
Additional details of IP support will be announced during 2006.
Samples of the first member of the LatticeECP2 family, the ECP2-50, will be made available during Q1 2006.
The LatticeECP2-50 will be offered in 484 and 672 ball fpBGA package options.
Lattice plans to introduce the entire LatticeECP2 family during 2006.
The ECP2-50 will be priced as low as $23.95 in 100,000 unit quantities for delivery in 2007.
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