Product category:
Measurement and Quality Software and SPC
News Release from: Synplicity | Subject: Synplify DSP software
Edited by the Manufacturingtalk Editorial
Team on 14 May 2004
Premiere Solution For DSP Designs In
FPGAs
With DSP software, users of the Simulink design environment from The MathWorks can automatically take designs specified at the algorithm level and generate high-quality, synthesis-ready RTL code.
Synplicity, supplier of software for the design and verification of semiconductors, has introduced Synplify DSP software, a premiere solution for implementing DSP designs in FPGAs With the Synplify DSP software, users of the Simulink design environment from The MathWorks can automatically take designs specified at the algorithm level and generate high-quality, synthesis-ready RTL code
This article was originally published on Manufacturingtalk on 4 Feb 2005 at 8.00am (UK)
Related stories
Software gridges DSP algorithm
Synplicity has unveiled enhancements to its Synplify DSP software, a premiere DSP synthesis solution for implementing DSP designs in FPGAs.
Automatic algorithm implementation
Synplify DSP ASIC Edition software allows users to automatically develop high-quality RTL code from designs specified at the algorithm level for implementation into either an FPGA or ASIC device
By utilizing unique system-level optimizations, the Synplify DSP software can produce circuits that are up to 50 percent faster and 30 percent smaller than solutions created by alternative tools for implementing DSP in hardware.
"Until now, there has been no automated way to get a design specified at the algorithm level, from tools such as The MathWorks' Simulink, into high-quality RTL code," said Jeff Garrison, director of marketing, Synplicity.
"A common approach was to hand off the RTL generation task to someone other than the DSP algorithm architect, resulting in numerous iterations.
Further reading
Synthesis platform achieves significant growth
True DSP synthesis methodology and close vendor partnerships drive adoption of new wireless IP
High-speed verification and total bug visibility
Synplicity revolutionises ASIC verification methodology with new TotalRecall technology
Optimal support for Xilinx Spartan-3A devices
Synplify Pro Software offers design tool advantages for new low-cost, high-volume devices.
This method is error prone and extremely time consuming.
With the Synplify DSP software, we're leveraging the widely used floating-point and fixed-point data types from The MathWorks to provide a single representation of the system design in Simulink.
The design is implemented from the fixed-point model that has been verified in the Simulink environment.
This removes ambiguity that can occur when manually writing RTL." "DSP designers are increasingly targeting FPGAs for implementation of high-performance DSP designs," said Ken Karnofsky, marketing director for DSP and communications products at The MathWorks.
"Synplicity has delivered sophisticated tools for users to generate high-quality RTL code from Simulink that not only delivers impressive QoR, but leverages the comprehensive DSP simulation and analysis already built into Simulink." Implementing DSP algorithms in hardware can result in an order of magnitude performance increase over standard DSP processors and with the growing demand for enhanced DSP performance for applications such as video/image processing, wireless networking, HDTV, set-top boxes and military and aerospace products, the rate of growth for hardware-based DSPs continues to rise.
System-Level Optimizations and Increased Productivity The new Synplify DSP software optimizes Simulink-based designs at the system level prior to RTL generation, using algorithms such as system-level re-timing that greatly improves performance of the DSP implementation.
Automatic multi-channelization addresses the time-consuming issue of deciding the optimum number of channels for a particular design.
With this patent-pending technique, the designer can perform a quick "what-if" analysis on thread capacity by automatically generating a multi-channel system from a single-channel specification, resulting in a simplified and faster design process.
The new software also uses a unique folding algorithm that allows the user to quickly trade off between performance and area.
Because DSP algorithms often consume large numbers of expensive hardware functions such as multipliers, the Synplify DSP tool automatically shares expensive resources within a performance budget.
The area/performance trade-off analysis is performed before the implementation process, saving design iterations and large amounts of circuit area.
In addition to generating high-quality RTL code, the Synplify DSP software also produces a test bench that can save designers additional time during the verification process.
The generated RTL model can then be verified in any HDL simulator using the stimulus from the Simulink environment.
The result is a single-source verification methodology from system model to gates.
Seamless Integration with The MathWorks Simulink Environment Included in the Synplify DSP software is a set of functional blocks commonly used in DSP design, such as filtering (FIR, IIR), transforms, math functions, CORDIC, signal operations, memories and control logic.
These technology-independent blocks are tightly integrated into The MathWorks environment, allowing the algorithm designer to continue to use familiar Simulink capabilities such as discrete-time simulation, multi-rate management, fixed point quantization and scope debugging.
With the Synplify DSP toolbox, users can automatically create high-quality RTL code and a test bench from Simulink specification.
• Synplicity: contact details and other news
• Email this article to a colleague
• Register for the free Manufacturingtalk email newsletter
• Manufacturingtalk Home Page
Search the Pro-Talk network of sites
